IS61DDPB24M18C Overview
at page 6 for each ODT option. These SRAMs have a mon I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
IS61DDPB24M18C Key Features
- 2Mx36 and 4Mx18 configuration available
- mon I/O read and write ports
- Max. 567 MHz clock for high bandwidth
- Synchronous pipeline read with self-timed late write
- Double Data Rate (DDR) interface for read and
- 2.5 cycle read latency
- Fixed 2-bit burst for read and write operations
- Two input clocks (K and K#) for address and control
- Two echo clocks (CQ and CQ#) that are delivered
- +1.8V core power supply and 1.5, 1.8V VDDQ, used
