Datasheet4U Logo Datasheet4U.com

IS61DDPB24M18 - DDR-IIP (Burst of 2) CIO Synchronous SRAMs

General Description

The 72Mb IS61DDPB22M36 and IS61DDPB24M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices.

These SRAMs have a common I/O bus.

The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.

Key Features

  • 2M x 36 or 4M x 18.
  • On-chip delay-locked loop (DLL) for wide data valid window.
  • Common data input/output bus.
  • Synchronous pipeline read with self-timed late write operation.
  • Double data rate (DDR-IIP) interface for read and write input ports.
  • Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K) for address and control registering at rising edges only.
  • Industrial te.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IS61DDPB24M18C 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM ISSI
IS61DDPB24M18C1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI
IS61DDPB24M18C2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM ISSI

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61DDPB24M18A 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18A1 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18A2 72Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB24M18B 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB24M18B1 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB24M18B2 72Mb DDR-IIP CIO SYNCHRONOUS SRAM
IS61DDPB21M18A 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M18A1 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M18A2 18Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM
IS61DDPB21M36A 36Mb DDR-IIP(Burst 2) CIO SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
72 Mb (2M x 36 & 4M x 18) DDR-IIP (Burs. t of 2) CIO Synchronous SRAMs (2.5 Cycle Read Latency) Advanced Information May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late write operation. • Double data rate (DDR-IIP) interface for read and write input ports. • Fixed 2-bit burst for read and write operations. • Clock stop support. • Two input clocks (K and K) for address and control registering at rising edges only. • Industrial temperature available upon request. • Two echo clocks (CQ and CQ) that are delivered simultaneously with data. • +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. • HSTL input and output levels.