IS61LF25632 Overview
The ISSI IS61LF25632, IS61LF25636, and IS61LF51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance and memories for mucation and networking applications. The IS61LF25632 is organized as 262,144 words by 32 bits and the IS61LF25636 is organized as 262,144 words by 36 bits. The IS61LF51218 is organized as 524,288 words by 18 bits.
IS61LF25632 Key Features
- Internal self-timed write cycle
- Individual Byte Write Control and Global Write
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control using MODE input
- Three chip enable option for simple depth expansion and address pipelining
- mon data inputs and data outputs
- JEDEC 100-Pin TQFP and 119-pin PBGA package
- Power Supply + 3.3V VDD + 3.3V or 2.5V VDDQ (I/0)
- Snooze MODE for reduced-power standby
- T version (three chip selects)