Datasheet Summary
IS61NLP6432A IS61NLP6436A/IS61NVP6436A IS61NLP12818A/IS61NVP12818A
64K x 32, 64K x 36, and 128K x 18 2Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
ISSI
SEPTEMBER 2005
®
PRELIMINARY INFORMATION
Features
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DESCRIPTION
The 2 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and munications applications. They are organized as 64K words by 32 bits, 64K words by 36 bits, and 128K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or...