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IS61NLP51218B - 9Mb STATE BUS SRAM

Download the IS61NLP51218B datasheet PDF. This datasheet also covers the IS61NLP25636B variant, as both devices belong to the same 9mb state bus sram family and are provided as variant models within a single manufacturer datasheet.

General Description

The 9 Meg product family

Key Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle.
  • Individual Byte Write Control.
  • Single R/W (Read/Write) control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control us- ing MODE input.
  • Three chip enables for simple depth expansion and address pipelining.
  • Power Down mode.
  • Common data inputs and data outp.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS61NLP25636B-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
IS61NLP51218 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM Integrated Silicon Solution Inc
IS61NLP102436A 36Mb STATE BUS SRAM Integrated Silicon Solution
IS61NLP204818A 36Mb STATE BUS SRAM Integrated Silicon Solution
IS61NLP204836B PIPELINE (NO WAIT) STATE BUS SRAM Integrated Silicon Solution
IS61NLP25632 256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM Integrated Silicon Solution Inc

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NLP51218B 9Mb STATE BUS SRAM
IS61NLP51218A 9Mb STATE BUS SRAM
IS61NLP51232B 18Mb STATE BUS SYNCHRONOUS SRAM
IS61NLP51236 (IS61NVPxxxxx) STATE BUS SRAM
IS61NLP51236B 18Mb STATE BUS SYNCHRONOUS SRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS61NLP25636B/IS61NVP/NVVP25636B IS61NLP51218B/IS61NVP/NVVP51218B  ® Long-term Support World Class Quality 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.