IS61NLP51218B Datasheet PDF - ISSI 9Mb STATE BUS SRAM Specs

IS61NLP51218B - 9Mb STATE BUS SRAM

This page provides the datasheet information for the IS61NLP51218B, a member of the IS61NLP25636B 9Mb STATE BUS SRAM family.

Datasheet Summary

Description

The 9 Meg product family

Features

100 percent bus utilization.
No wait cycles between Read and Write.
Internal self-timed write cycle.
Individual Byte Write Control.
Single R/W (Read/Write) control pin.
Clock controlled, registered address, data and control.
Interleaved or linear burst sequence control us- ing MODE input.
Three chip enables for simple depth expansion and address pipelining.
Power Down mode.
Common data inputs and data outp.

Datasheet Details

Part number	IS61NLP51218B
Manufacturer	ISSI
File Size	940.52 KB
Description	9Mb STATE BUS SRAM
Datasheet	IS61NLP51218B Datasheet
Additional preview pages of the IS61NLP51218B datasheet.

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Full PDF Text Transcription

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IS61NLP25636B/IS61NVP/NVVP25636B IS61NLP51218B/IS61NVP/NVVP51218B ® Long-term Support World Class Quality 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM AUGUST 2019 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control us- ing MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin QFP, 165-ball BGA and 119-ball BGA packages • Power supply: NLP: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) NVP: Vdd 2.

Published: Feb 18, 2024 |