Datasheet Summary
IS61NVP51236 IS61NVP10018
512K x 36 and 1M x 18 PIPELINE 'NO WAIT' STATE BUS SRAM
Features
- 100 percent bus utilization
- No wait cycles between Read and Write
- Internal self-timed write cycle ..
- Individual Byte Write Control
- Single R/W (Read/Write) control pin
- Clock controlled, registered address, data and control
- Interleaved or linear burst sequence control using MODE input
- Three chip enables for simple depth expansion and address pipelining for TQFP
- Power Down mode
- mon data inputs and data outputs
- CKE pin to enable clock and suspend operation
- JEDEC 100-pin TQFP, 119 PBGA package
- VDD +2.5V power supply (± 5%)
- VDDQ: 2.5V I/O Supply Voltage
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