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IS61NVP10018 - (IS61NVP10018 / IS61NVP51236) State Bus SRAM

General Description

The 18 Meg 'NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers.

Key Features

  • 100 percent bus utilization.
  • No wait cycles between Read and Write.
  • Internal self-timed write cycle www. DataSheet4U. com.
  • Individual Byte Write Control.
  • Single R/W (Read/Write) control pin.
  • Clock controlled, registered address, data and control.
  • Interleaved or linear burst sequence control using MODE input.
  • Three chip enables for simple depth expansion and address pipelining for TQFP.
  • Power Down mode.
  • Commo.

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61NVP102418 (IS61NVPxxxxx) STATE BUS SRAM
IS61NVP102418B 18Mb STATE BUS SYNCHRONOUS SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61NVP51236 IS61NVP10018 512K x 36 and 1M x 18 PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle www.DataSheet4U.com • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining for TQFP • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 119 PBGA package • VDD +2.5V power supply (± 5%) • VDDQ: 2.