IS61QDB21M18A Description
The and are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed.
IS61QDB21M18A Key Features
- 512Kx36 and 1Mx18 configuration available
- On-chip Delay-Locked Loop (DLL) for wide data
- Synchronous pipeline read with EARLY write
- Double Data Rate (DDR) interface for read and
- Fixed 2-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control
- Two output clocks (C and C#) for data output control
- Two echo clocks (CQ and CQ#) that are delivered
- +1.8V core power supply and 1.5, 1.8V VDDQ, used