IS61QDB21M18C Datasheet | ISSI

FEATURES - 512Kx36 and 1Mx18 configuration available. - On-chip Delay-Locked Loop (DLL) for wide data valid window. - Separate independent read and write ports with concurrent read and write operations. - Synchronous pipeline read with EARLY write operation. - Double Data Rate (DDR) interface for read and write input ports. - Fixed 2-bit burst for read and write operations. - Clock stop support. - Two input clocks (K and K#) for address and control registering at rising edges only. - Two output clocks (C and C#) for data output control. - Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. - +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF. - HSTL input and output interface. - Registered addresses, write and read controls, byte writes, data in, and data outputs. - Full data coherency. - Boundary scan using limited set of JTAG 1149.1 functions. - Byte write capability. - Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array - Programmable impedance output drivers via 5x user-supplied precision resistor. DESCRIPTION The 18Mb IS61QDB251236C and IS61QDB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 2) SRAMs. The input address bus operates at double data rate. The following are registered internally on the rising edge of the K clock: - Read address - Read enable - Write enable - Byte writes - Data-in for early writes The following are registered on the rising edge of the K# clock: - Write address - Byte writes - Data-in for second burst addresses Byte writes can change with the corresponding data-in to enable or disable writes on a...