IS61QDP2B42M18A2 Overview
These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs.
IS61QDP2B42M18A2 Key Features
- 1Mx36 and 2Mx18 configuration available
- On-chip Delay-Locked Loop (DLL) for wide data valid window
- Separate independent read and write ports with concurrent read and write operations
- Synchronous pipeline read with late write operation
- Double Data Rate (DDR) interface for read and write input ports
- 2.0 cycle read latency
- Fixed 4-bit burst for read and write operations
- Clock stop support
- Two input clocks (K and K#) for address and control registering at rising edges only
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data