IS61QDP2B42M36A Datasheet PDF - ISSI 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM Specs

IS61QDP2B42M36A - 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM

This page provides the datasheet information for the IS61QDP2B42M36A, a member of the IS61QDP2B44M18A 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM family.

Datasheet Summary

Description

2Mx36 and 4Mx18 configuration available.

On-chip Delay-Locked Loop (DLL) for wide data valid window.

Separate independent read and write ports with concurrent read and write operations.

Synchronous pipeline read with late write operation.

Double Data Rate (DDR) interfa

Datasheet Details

Part number	IS61QDP2B42M36A
Manufacturer	ISSI
File Size	645.11 KB
Description	72Mb QUADP (Burst 4) SYNCHRONOUS SRAM
Datasheet	IS61QDP2B42M36A Datasheet
Additional preview pages of the IS61QDP2B42M36A datasheet.

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Full PDF Text Transcription

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IS61QDP2B44M18A/A1/A2 IS61QDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb QUADP (Burst 4) SYNCHRONOUS SRAM (2.0 Cycle Read Latency) DECEMBER 2014 FEATURES DESCRIPTION  2Mx36 and 4Mx18 configuration available.  On-chip Delay-Locked Loop (DLL) for wide data valid window.  Separate independent read and write ports with concurrent read and write operations.  Synchronous pipeline read with late write operation.  Double Data Rate (DDR) interface for read and write input ports.  2.0 cycle read latency.  Fixed 4-bit burst for read and write operations.  Clock stop support.  Two input clocks (K and K#) for address and control registering at rising edges only.  Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.  Data Valid Pin (QVLD).  +1.8V core power supply and 1.5, 1.

Published: Jun 10, 2016 |