IS61QDPB44M18
Overview
The 72Mb IS61QDPB42M36 and IS61QDPB44M18 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround.
- 2M x 36 or 4M x 18.
- On-chip delay-locked loop (DLL) for wide data valid window.
- Separate read and write ports with concurrent read and write operations.
- Synchronous pipeline read with late write operation.
- Double data rate (DDR) interface for read and write input ports.
- Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K) for address and control registering at rising edges only.
- Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
- +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
