IS61QDPB44M18B2
Overview
- 2Mx36 and 4Mx18 configuration available.
- On-chip Delay Locked Loop (DLL) for wide data valid window.
- Separate independent read and write ports with concurrent read and write operations.
- Synchronous pipeline read with late write operation.
- Double Data Rate (DDR) interface for read and write input ports.
- 2.5 cycle read latency.
- Fixed 4-bit burst for read and write operations.
- Clock stop support.
- Two input clocks (K and K#) for address and control registering at rising edges only.
- Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
