Datasheet Summary
ISSI®
64K x 32 SYNCHRONOUS PIPELINE STATIC RAM
JUNE 2001
Features
- Internal self-timed write cycle
- Individual Byte Write Control and Global Write
- Clock controlled, registered address, data and control
- Pentium™ or linear burst sequence control using
MODE input
- Three chip enables for simple depth expansion and address pipelining
- mon data inputs and data outputs
- Power-down control by ZZ input
- JEDEC 100-Pin TQFP and PQFP package
- Single +3.3V power supply
- Two Clock enables and one Clock disable to eliminate multiple bank bus contention
- Control pins mode upon power-up:
- MODE in interleave burst mode
- ZZ in normal operation mode These control pins can be...