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IS61SPS25632D - 256Kx32 Synchronous Pipelined Static RAM

General Description

IS61LPS25632, IS61LPS25636, and IS61LPS51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance memory for communication and networking applications.

Key Features

  • Internal self-timed write cycle.
  • Individual Byte Write Control and Global Write.
  • Clock controlled, registered address, data and control.
  • Linear burst sequence control using MODE input.
  • Three chip enable option for simple depth expansion and address pipelining.
  • Common data inputs and data outputs.
  • JEDEC 100-Pin TQFP and 119-pin PBGA package.
  • Single +3.3V, +10%,.
  • 5% power supply.
  • Power-down snooze mode.

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📁 Similar Datasheet

Part Number Description Manufacturer
IS61SP12832 128K x 32 SYNCHRONOUS PIPELINED STATIC RAM Integrated Circuit Solution
IS61SP6464 64K x 64 SYNCHRONOUS PIPELINE STATIC RAM Integrated Silicon Solution Inc
IS61SPD25632T 256K x 32/ 256K x 36/ 512K x 18 SYNCHRONOUS PIPELINE/ DOUBLE-CYCLE DESELECT STATIC RAM Integrated Silicon Solution Inc
IS61SF12832 (IS61SF12832 / IS61SF12836) 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM Integrated Silicon Solution
IS61SF12836 (IS61SF12832 / IS61SF12836) 128K x 36 SYNCHRONOUS FLOW-THROUGH STATIC RAM Integrated Silicon Solution

Other Datasheets by ISSI (now Infineon)

Part Number Description
IS61SPS25632T 256Kx32 Synchronous Pipelined Static RAM
IS61SPS25636D 256Kx32 Synchronous Pipelined Static RAM
IS61SPS25636T 256Kx32 Synchronous Pipelined Static RAM
IS61SPS51218D 256Kx32 Synchronous Pipelined Static RAM
IS61SPS51218T 256Kx32 Synchronous Pipelined Static RAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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IS61SPS25632T/D IS61LPS25632T/D IS61SPS25636T/D IS61LPS25636T/D IS61SPS51218T/D IS61LPS51218T/D 256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, SINGLE-CYCLE DESELECT STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Linear burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • JEDEC 100-Pin TQFP and 119-pin PBGA package • Single +3.3V, +10%, –5% power supply • Power-down snooze mode • 3.3V I/O For SPS • 2.