IS61WV3216BLL Datasheet | ISSI

FEATURES - High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V - CMOS low power operation: 50 m W (typical) operating 25 µW (typical) standby - TTL patible interface levels - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Automotive Temperature Available - Lead-free available DESCRIPTION The ISSI IS61/64WV3216BLL is a high-speed, 524,288-bit static RAM organized as 32,768 words by 16 bits. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12ns (3.3V + 10%) and 15ns (2.5V-3.6V) with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. Data Shee The IS61/64WV3216BLL is packaged in the JEDEC stan. dard 44-pin TSOP-II, and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT . Rev. A 09/26/05 Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. - .issi. - 1-800-379-4774 Data Sheet 4 U . .. IS64WV3216BLL IS61WV3216BLL PIN...