IS61WV3216DBLS Datasheet | ISSI

FEATURES HIGH SPEED: (IS61/64WV3216DBLL) - High-speed access time: 8, 10, 12, 20 ns - Low Active Power: 135 m W (typical) - Low Standby Power: 12 µW (typical) CMOS standby LOW POWER: (IS61/64WV3216DBLS) - High-speed access time: 25, 35 ns - Low Active Power: 55 m W (typical) - Low Standby Power: 12 µW (typical) CMOS standby - Single power supply - Vdd 2.4V to 3.6V (IS61/64WV3216DBxx) - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Industrial and Automotive temperature support - Lead-free available DESCRIPTION The ISSI IS61WV3216DBLx and IS64WV3216DBLx are high-speed, 524,288-bit static RAMs organized as 32,768 words by 16 bits. It is fabricated using ISSI's high- performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61WV3216DBLx and IS64WV3216DBLx are packaged in the JEDEC standard 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A14 DECODER 32K x 16 MEMORY ARRAY VDD GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CONTROL CIRCUIT Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on...