IS62LV12816BLL Datasheet | ISSI

FEATURES - High-speed access time: 55, 70, 100 ns - CMOS low power operation - 120 m W (typical) operating - 6 µW (typical) CMOS standby - TTL patible interface levels - Single 2.7V-3.45V VCC power supply - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Industrial temperature available - Available in the 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm) ISSI DESCRIPTION ® FEBRUARY 2001 The ISSI IS62LV12816BLL is a high-speed, 2,097,152-bit static RAM organized as 131,072 words by 16 bits. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected) or when CE is low and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS62LV12816BLL is packaged in the JEDEC standard 44-pin TSOP (Type II) and 48-pin mini BGA (6mm x 8mm). FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 16 MEMORY ARRAY VCC GND I/O0-I/O7 Lower Byte I/O8-I/O15 Upper Byte I/O DATA CIRCUIT COLUMN I/O CE OE WE UB LB CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. - 1-800-379-4774 Rev. B 03/07/01 PIN CONFIGURATIONS 44-Pin TSOP (Type II) A4 A3 A2 A1 A0 CE I/O0 I/O1 I/O2 I/O3 Vcc GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12 1 2 3 4 5 6...