IS62WV102416GBLL Datasheet | ISSI

FEATURES - High-speed access time: 45ns, 55ns - CMOS low power operation - Operating Current: 35m A (max.) - CMOS standby Current: 5.5u A (typ.) - TTL patible interface levels - Single power supply - 1.65V-2.2V VDD (IS62/65WV102416GALL) - 2.2V-3.6V VDD (IS62/65WV102416GBLL) - Three state outputs - mercial, Industrial and Automotive temperature support - Lead-free available FUNCTIONAL Block Diagram A0 - A19(20) DECODER VDD GND I/O0 - I/O7 Lower Byte I/O8 - I/O15 Upper Byte I/O DATA CIRCUIT BYTE# CS2 CS1# OE# WE# UB# LB# CONTROL CIRCUIT 1024K x 16 (2048Kx8) MEMORY ARRAY COLUMN I/O DESCRIPTION The ISSI IS62/65WV102416GALL/BLL are high-speed, low power, 16M bit static RAMs organized as 1024K words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CS1# is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1# is LOW, CS2 is HIGH and both LB# and UB# are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE#) controls both writing and reading of the memory. A data byte allows Upper Byte (UB#) and Lower Byte (LB#) access. The device supports 16 I/Os when BYTE# is High, and 8 I/Os when BYTE# is Low. In x8 mode, UB#, LB#, and I/O8~I/O14 are not used, and I/O15 bees A20. The IS62/65WV102416GALL/BLL are packaged in the JEDEC standard 48-Pin TSOP (TYPE I) . Copyright © 2020 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device...