IS64C5128AL Datasheet | ISSI

FEATURES HIGH SPEED: (IS61/64C5128AL) - High-speed access time: 10ns, 12 ns - Low Active Power: 150 m W (typical) - Low Standby Power: 10 m W (typical) CMOS standby LOW POWER: (IS61/64C5128AS) - High-speed access time: 25ns - Low Active Power: 75 m W (typical) - Low Standby Power: 1 m W (typical) CMOS standby - TTL patible interface levels - Single 5V ± 10% power supply - Fully static operation: no clock or refresh required - Available in 36-pin SOJ (400-mil), 32-pin s TSOP-I, 32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages - mercial, Industrial and Automotive temperature ranges available - Lead-free available DESCRIPTION The ISSI IS61C5128AL/AS and IS64C5128AL/AS are high- speed, 4,194,304-bit static RAMs organized as 524,288 words by 8 bits. They are fabricated using ISSI's high- performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 12 ns with low power consumption. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61C5128AL/AS and IS64C5128AL/AS are packaged in the JEDEC standard 36-pin SOJ (400-mil), 32-pin s TSOP-I, 32-pin SOP, 44-pin TSOP-II and 32-pin TSOP-II packages FUNCTIONAL BLOCK DIAGRAM A0-A18 VDD GND I/O0-I/O7 DECODER I/O DATA CIRCUIT 512K X 8 MEMORY ARRAY COLUMN I/O CONTROL CIRCUIT Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised...