IS64LPS12832EC Datasheet PDF - ISSI SINGLE CYCLE DESELECT SRAM Specs

IS64LPS12832EC - SINGLE CYCLE DESELECT SRAM

This page provides the datasheet information for the IS64LPS12832EC, a member of the IS61LPS12836EC SINGLE CYCLE DESELECT SRAM family.

Datasheet Summary

Description

The 4Mb product family

Features

Internal self-timed write cycle.
Individual Byte Write Control and Global Write.
Clock controlled, registered address, data and control.
Burst sequence control using MODE input.
Three chip enable option for simple depth expansion and address pipelining.
Common data inputs and data outputs.
Auto Power-down during deselect.
Single cycle deselect.
Snooze MODE for reduced-power standby.
JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages.

Datasheet Details

Part number	IS64LPS12832EC
Manufacturer	ISSI
File Size	2.16 MB
Description	SINGLE CYCLE DESELECT SRAM
Datasheet	IS64LPS12832EC Datasheet
Additional preview pages of the IS64LPS12832EC datasheet.

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Full PDF Text Transcription

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IS61(4)LPS12836EC/IS61(4)VPS12836EC/IS61(4)LPS12832EC IS61(4)VPS12832EC/IS61(4)LPS25618EC/IS61(4)VPS25618EC 128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM APRIL 2017 FEATURES  Internal self-timed write cycle  Individual Byte Write Control and Global Write  Clock controlled, registered address, data and control  Burst sequence control using MODE input  Three chip enable option for simple depth expansion and address pipelining  Common data inputs and data outputs  Auto Power-down during deselect  Single cycle deselect  Snooze MODE for reduced-power standby  JEDEC 100-pin QFP, 165-ball BGA and 119- ball BGA packages  Power supply: LPS: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) VPS: VDD 2.5V (± 5%), VDDQ 2.

Published: Nov 7, 2016 |