IS64WV25616EDBLL Datasheet | ISSI

IS61WV25616EDBLL IS64WV25616EDBLL 256K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC JULY 2020 Features - High-speed access time: 8, 10 ns - Low Active Power: 85 m W (typical) - Low Standby Power: 7 m W (typical) CMOS standby - Single power supply - Vdd 2.4V to 3.6V (10 ns) - Vdd 3.3V ± 10% (8 ns) - Fully static operation: no clock or refresh required - Three state outputs - Data control for upper and lower bytes - Industrial and Automotive temperature support - Lead-free available - Error Detection and Error Correction FUNCTIONAL BLOCK DIAGRAM DESCRIPTION The ISSI IS61/64WV25616EDBLL is a high-speed, 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields highperformance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IS61/64WV25616EDBLL is packaged in the JEDEC standard 44-pin TSOP-II and 48-pin Mini BGA (6mm x 8mm). A0-A17 Decoder Memory Lower IO Array256Kx8 ECC Array256K x4 Memory Upper IO...