IS66WVH8M8FALL Datasheet | ISSI

Overview PRELIMINARY INFORMATION JANUARY 2024 The IS66/67WVH8M8FALL/BLL are integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a Hyper Bus interface, Very Low Signal Count (Address, mand and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed especially for Mobile and Automotive applications. Distinctive Characteristics Hyper Bus TM Low Signal Count Interface - 1.8 V / 3.0 V interface support o Single-ended clock (CK) - 11 bus signals o Optional differential clock (CK, CK#) 12 bus signals - Chip Select (CS#) - 8-bit data bus (DQ[7:0]) - Read-Write Data Strobe (RWDS) o Bidirectional Data Strobe / Mask o Output at the start of all transactions to indicate refresh latency o Output during read transactions as Read Data Strobe - Configurable output drive strength Performance Summary Read Transaction Timings Maximum Clock Rate at 1.8V 200 MHz VCC/VCCQ Maximum Clock Rate at 3.0V 200 MHz VCC/VCCQ Maximum Access Time 35 ns High Performance - 200Mhz maximum clock rate - Double-Data Rate (DDR) - two data transfers per clock - Data throughput up to 400 MB/s (3,200 Mbps) o Configurable Burst Characteristics Wrapped burst lengths: - 16 bytes (8 clocks) - 32 bytes (16 clocks) - 64 bytes (32 clocks) - 128 bytes (64 clocks) o Linear burst o Hybrid burst - one wrapped burst followed by linear burst - Power Modes o Hybrid Sleep Mode o Deep Power Down - Array Refresh o Partial Array (1/8, 1/4, 1/2, and so on) o Full Array - Temperature Grade o Industrial: -40°C to +85°C o Auto (A2) Grade: -40°C to +105°C - Package o 24-ball FBGA o Green Package (Ro HS pliant, Halogen-Free) and TSCA pliant Maximum Current Consumption Burst Read or Write (linear burst at 200 MHz, 1.8V) Burst Read or Write (linear burst at 200 MHz, 3.0V) Standby (CS# = High, 3V, 105 °C) Deep Power Down (CS# = High, 3V, 105 °C) Standby (CS# = High, 1.8V,...