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IS67WVE51216EALL - 8Mb Async/Page PSRAM

Download the IS67WVE51216EALL datasheet PDF. This datasheet also covers the IS66WVE51216EALL variant, as both devices belong to the same 8mb async/page psram family and are provided as variant models within a single manufacturer datasheet.

General Description

PSRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable applications.

The 8Mb DRAM core device is organized as 512K x 16 bits.

Key Features

  • Asynchronous and page mode interface.
  • Dual voltage rails for optional performance.
  • ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V.
  • BLL: VDD 2.7V~3.6V, VDDQ 2.7V~3.6V.
  • CLL: VDD 1.7V~1.95V, VDDQ 2.7V~3.6V.
  • Page mode read access.
  • Interpage Read access : 60ns, 70ns.
  • Intrapage Read access : 25ns.
  • Low Power Consumption.
  • Asynchronous Operation < 30 mA.
  • Intrapage Read < 23 mA.
  • Standby < 150 uA (max. ).
  • Deep power-down (DPD).
  • ALL/CLL: < 3µA (Typ.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IS66WVE51216EALL-ISSI.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by ISSI (now Infineon)

Part Number Description
IS67WVE51216EBLL 8Mb Async/Page PSRAM
IS67WVE51216ECLL 8Mb Async/Page PSRAM
IS67WVE51216TALL 8Mb Async/Page PSRAM
IS67WVE51216TBLL 8Mb Async/Page PSRAM
IS67WVE51216TCLL 8Mb Async/Page PSRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
IS66/IS67WVE51216EALL/EBLL/ECLL IS67/IS67WVE51216TALL/TBLL/TCLL 8Mb Async/Page PSRAM NOVEMBER 2015 Overview The IS66/67WVE51216EALL/BLL/CLL and IS66/67WVE51216TALL/BLL/CLL are integrated memory device containing 8Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 512K words by 16 bits. The device includes several power saving modes : Partial Array Refresh mode where data is retained in a portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from the device core. Features  Asynchronous and page mode interface  Dual voltage rails for optional performance  ALL: VDD 1.7V~1.95V, VDDQ 1.7V~1.95V  BLL: VDD 2.7V~3.