IS67WVH8M8FALL
Overview
PRELIMINARY INFORMATION
JANUARY 2024
The IS66/67WVH8M8FALL/BLL are integrated memory device containing 64Mbit Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a Hyper Bus interface, Very Low Signal Count (Address, mand and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation, designed especially for Mobile and Automotive applications.
Distinctive Characteristics
Hyper Bus TM Low Signal Count Interface
- 1.8 V / 3.0 V interface support o Single-ended clock (CK)
- 11 bus signals o Optional differential clock (CK, CK#) 12 bus signals
- Chip Select (CS#)
- 8-bit data bus (DQ[7:0])
- Read-Write Data Strobe (RWDS) o Bidirectional Data Strobe / Mask o Output at the start of all transactions to indicate refresh latency o Output during read transactions as Read Data Strobe
- Configurable output drive strength
Performance Summary
Read Transaction Timings
Maximum Clock Rate at...
