IXTH36P10 Description
+150 °C 300 °C 1.13/10 Nm/lb.in. 6 g TO-247 AD D (TAB) G = Gate, S = Source, D = Drain, TAB = Drain.
IXTH36P10 Key Features
- International standard package
- Low RDS (on) HDMOSTM process
- Rugged polysilicon gate cell structure
- Unclamped Inductive Switching (UIS)
- Low package inductance (<5 nH)
- easy to drive and to protect
- 3.0 TJ = 25°C TJ = 125°C