HYB18T1G400AF Overview
Edition 2004-05-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany © Infineon Technologies AG 5/7/04. The information herein is given to describe certain ponents and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved.
HYB18T1G400AF Key Features
- High Performance
- 5 -400 -3.7 -533 -3S -667 -3
- 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) patible) I/O
- DRAM organisations with 4, 8 and 16 data in/outputs
- Double Data Rate architecture: two data transfers per clock cycle, eight internal banks for concurrent operation
- CAS Latency: 3, 4 and 5
- Burst Length: 4 and 8
- Differential clock inputs (CK and CK)
- Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read dat
- DLL aligns DQ and DQS transitions with clock
