HYB18T1G400AF Datasheet | Infineon

atures - High Performance: -5 -400 -3.7 -533 -3S -667 -3 1Gb DDR2 SDRAM Speed Sorts DDR2 DDR2 DDR2 DDR2 -667 Units tck MHz Mb/s/pin Bin (CL-t RCD-TRP) max. Clock Frequency 3-3-3 4-4-4 5-5-5 4-4-4 200 400 3 15 15 40 55 266 533 4 15 15 45 60 5 15 15 45 60 333 667 4 12 12 45 57 Data Rate CAS Latency (CL) t RCD t RP t RAS t RC tck ns ns ns ns - 1.8V ± 0.1V Power Supply 1.8 V ± 0.1V (SSTL_18) patible) I/O - DRAM organisations with 4, 8 and 16 data in/outputs - Double Data Rate architecture: two data transfers per clock cycle, eight internal banks for concurrent operation - CAS Latency: 3, 4 and 5 - Burst Length: 4 and 8 - Differential clock inputs (CK and CK) - Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data - DLL aligns DQ and DQS transitions with clock - DQS can be disabled for single-ended data strobe operation - mands entered on each positive clock edge, data and data mask are referenced to both edges of DQS - Data masks (DM) for write data - Posted CAS by programmable additive latency for better mand and...