HYB25D256800BT - 256MBit Double Data Rata SDRAM

Product Overview

Infineon Technologies AG

Part number	HYB25D256800BT
Manufacturer	Infineon Technologies AG
File Size	522.55 KB
Description	256MBit Double Data Rata SDRAM
Datasheet	HYB25D256800BT Datasheet
Note	This datasheet PDF includes multiple part numbers: HYB25D256800BT, HYB-25D. Please refer to the document for exact specifications by model.
Additional preview pages of the HYB25D256800BT datasheet.

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

It is internally configured as a quad-bank DRAM.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation.

CAS Latency and Clock Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400B DDR400A -5 -5A 133 133 166 200 200 200.
Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is center-aligned with data for writes.
Differential clock inputs (CK and CK).
Four internal.

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Published: Apr 3, 2005 |