HYB25D256800BC - 256-Mbit Double Data Rate SDRAM

This page provides the datasheet information for the HYB25D256800BC, a member of the HYB25D256400BT 256-Mbit Double Data Rate SDRAM family.

Product Overview

Infineon

Part number	HYB25D256800BC
Manufacturer	Infineon
File Size	2.15 MB
Description	256-Mbit Double Data Rate SDRAM
Datasheet	HYB25D256800BC Datasheet
Additional preview pages of the HYB25D256800BC datasheet.

CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166.
Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is center-aligned with data for writes.
Differential clock inputs (CK and CK).

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Published: Jul 21, 2018 |