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HYB25D256160BC - 256-Mbit Double Data Rate SDRAM

Download the HYB25D256160BC datasheet PDF. This datasheet also covers the HYB25D256400BT variant, as both devices belong to the same 256-mbit double data rate sdram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166.
  • Double data rate architecture: two data transfers per clock cycle.
  • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
  • DQS is edge-aligned with data for reads and is center-aligned with data for writes.
  • Differential clock inputs (CK and CK).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYB25D256400BT_InfineonTechnologiesAG.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. B Data Sheet Jan. 2003, V1.1 Features CAS Latency and Frequency CAS Latency 2 2.