HYB25D256160BT Datasheet | Infineon

Features CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz) DDR200 DDR266A DDR266 DDR333 -8 -7 -7F -6 100 133 133 133 125 143 143 166 - Double data rate architecture: two data transfers per clock cycle - Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - DQS is edge-aligned with data for reads and is center-aligned with data for writes - Differential clock inputs (CK and CK) - Four internal banks for concurrent operation - Data mask (DM) for write data - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS - Burst Lengths: 2, 4, or 8 - CAS Latency: (1.5), 2, 2.5, (3) - Auto Precharge option for each burst access - Auto Refresh and Self Refresh Modes - 7.8ms...