Infineon Technologies S25FL064L
The FL-L family devices are flash non-volatile memory products using: • Floating gate technology • 65-nm process lithography The FL-L family connects to a host system via a serial peripheral interface (SPI). The architecture features a page programming buffer that allows up to 256 bytes to be programmed in one operation and provides individual 4 KB sector, 32 KB half block sector, 64 KB block sector, or entire chip erase.FEATURES
● Serial peripheral interface (SPI) with multi-I/O - Clock polarity and phase modes 0 and 3 - Double data rate (DDR) option - Quad peripheral interface (QPI) option - Extended addressing: 24- or 32- bit address options - Serial command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S, and S25FS-S SPI families - Multi I/O command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families● Read - Commands: Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR Quad I/O - Modes: Burst wrap, Continuous (XIP), QPI - Serial flash discoverable parameters (SFDP) for configuration information
● Program architecture - 256-bytes page programming buffer - Program suspend and resume
● Erase architecture - Uniform 4 KB sector erase - Uniform 32 KB half block erase - Uniform 64 KB block erase - Chip erase - Erase suspend and resume
● 100,000 program-erase cycles, minimum
● 20 year data retention, minimum Datasheet Please read the Important Notice and...