S25HS02GT Datasheet | Infineon

overview - Architecture - Infineon 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell - Multi-chip package (MCP) - 02GT Dual Die Package (DDP) 2 × 1 Gb die - 04GT Quad Die Package (QDP) 4 × 1 Gb die - Sector Architecture options - Uniform - Address space consists of all 256 KB Sectors - Hybrid Configuration 1: Address space consists of thirty-two 4 KB sectors grouped either on the top or the bottom while the remaining sectors are all 256 KB Configuration 2: Address space consists of thirty-two 4 KB sectors at the top and bottom while the remaining sectors are all 256 KB - Page Programming buffer of 256 or 512 bytes - OTP Secure Silicon array of 1024 bytes (32 × 32 bytes) - Interface - Quad SPI - Supports 1S-1S-4S, 1S-4S-4S, 1S-4D-4D, 4S-4S-4S, 4S-4D-4D protocols - SDR option runs up to 83 MBps (166 MHz clock speed) - DDR option runs up to 102 MBps (102 MHz clock speed) - Dual SPI - Supports 1S-2S-2S protocol - SDR option runs up to 41.5 MBps (166 MHz clock speed) - SPI - Supports 1S-1S-1S protocol - SDR option runs up to 21 MBps (166 MHz clock speed) - Highlights - Safety features - Functional Safety with the Industry’s first ISO26262 ASIL B pliant and ASIL D ready NOR flash - Endura Flex™ Architecture provides High-Endurance and Long Retention Partitions - Data Integrity CRC detects errors in memory array - Safe Boot reports device initialization failures, detects configuration corruption and provides recovery options - Built-in Error Correcting Code (ECC) corrects Single-bit Error and detects Double-bit Error (SECDED) on memory array data - Sector Erase Status indicator for power loss during erase - Protection features - Legacy Block Protection for memory array and device configuration - Advanced Sector Protection for individual memory array sector based protection - Hardware Reset through CS# Signaling method (JEDEC) / individual RESET# pin / DQ3_RESET# pin Summary Datasheet .infineon. Please read the Important Notice and Warnings at...