74AUC1G02 Overview
74AUC1G02 The 74AUC1G02is a high-performance, low-power, low-voltage, Si-gate CMOS device. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. This device is fully specified for partial power-down applications using Ioff.
74AUC1G02 Key Features
- Wide supply voltage range from 0.8 to 2.7 V
- Performance optimised for VCC = 1.8 V
- High noise immunity
- plies with JEDEC standard
- JESD76 (1.65 to 1.95 V)
- 8 mA output drive (VCC = 1.65 V)
- CMOS low power consumption
- Latch-up performance exceeds 250 mA
- ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A)
- 3.3 V tolerant inputs/outputs