74AUC1G02GW Datasheet PDF (74AUC1G02 Single 2-input NOR gate) | Download Integrated Circuit Solution Inc 74AUC1G02GW

74AUC1G02GW - 74AUC1G02 Single 2-input NOR gate

Description

The 74AUC1G02is a high-performance, low-power, low-voltage, Si-gate CMOS device.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using Ioff.

Features

Wide supply voltage range from 0.8 to 2.7 V.
Performance optimised for VCC = 1.8 V.
High noise immunity.
Complies with JEDEC standard:.
JESD76 (1.65 to 1.95 V).
8 mA output drive (VCC = 1.65 V).
CMOS low power consumption.
Latch-up performance exceeds 250 mA.
ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A).
3.3 V tolerant inputs/outputs.
SC-88A and SC-74A package. Q.

Datasheet Details

Part number	74AUC1G02GW
Manufacturer	Integrated Circuit Solution Inc
File Size	50.08 KB
Description	74AUC1G02 Single 2-input NOR gate
Datasheet	74AUC1G02GW Datasheet
Additional preview pages of the 74AUC1G02GW datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS DATA SHEET 74AUC1G02 Single 2-input NOR gate Preliminary speciﬁcation File under Integrated Circuits, IC24 2002 Nov 12 Philips Semiconductors Preliminary speciﬁcation Single 2-input NOR gate FEATURES • Wide supply voltage range from 0.8 to 2.7 V • Performance optimised for VCC = 1.8 V • High noise immunity • Complies with JEDEC standard: – JESD76 (1.65 to 1.95 V) • 8 mA output drive (VCC = 1.65 V) • CMOS low power consumption • Latch-up performance exceeds 250 mA • ESD protection: 2000 V Human Body Model (A 114-A) 200 V Machine Model (A 115-A) • 3.3 V tolerant inputs/outputs • SC-88A and SC-74A package. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; input slewrate ≥ 1 V/ns. SYMBOL tPHL/tPLH PARAMETER propagation delay inputs A and B to output Y CONDITIONS VCC = 0.

Published: Apr 3, 2005 |