M2006-12 Overview
The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and...
M2006-12 Key Features
- Pin-selectable PLL divider ratios support forward
- 255/238 (OTU1) Mapping and 238/255 De-mapping
- 255/237 (OTU2) Mapping and 237/255 De-mapping
- 255/236 (OTU3) Mapping and 236/255 De-mapping
- Supports input reference and VCSO frequencies up
