M2006-12 Datasheet | Integrated Circuit Solution Inc

DESCRIPTION The M2006-02 and -12 are VCSO (Voltage Controlled SAW Oscillator) based clock generator PLLs designed for clock frequency translation and jitter attenuation. They support both forward and inverse FEC (Forward Error Correction) clock multiplication ratios, which are pin-selected from pre-programming look-up tables. The M2006-12 adds Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV pliance during reference clock reselection. Hitless Switching (HS) engages when a 4ns or greater clock phase change is detected. This phase-change triggered implementation of HS is not remended when using an unstable reference (more than 1ns jitter pk-to-pk) or when the resulting phase detector frequency is less than 5MHz. Refer to full product data sheet for more information. 27 26 25 24 23 22 21 20 19 28 29 30 31 32 33 34 35 36 M2006-02 M2006-12 (Top View) 18 17 16 15 14 13 12 11 10 P0_SEL P1_SEL n FOUT0 FOUT0 GND n FOUT1 FOUT1 VCC GND FEATURES - Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation, including: - 255/238 (OTU1) Mapping and 238/255 De-mapping - 255/237 (OTU2) Mapping and 237/255 De-mapping - 255/236 (OTU3) Mapping and 236/255 De-mapping Example I/O Clock Frequency binations Using M2006-02/-12-622.0800 and Inverse FEC Ratios FEC PLL Ratio Mfec / Rfec 1/1 238/255 237/255 236/255 Base Input Rate 1 (MHz) 622.0800 666.5143 669.3266 672.1627 Output Clock (either output) MHz 622.08 or 155.52 - Supports input reference and VCSO frequencies up - - - - - to 700MHz, supports loop timing modes (Specify VCSO frequency at time of order) Low phase jitter < 0.5 ps rms typical (12k Hz to 20MHz or 50k Hz to 80MHz) M2006-12 includes APC pin for Phase Build-out function (for absorption of the input phase change) mercial and Industrial temperature grades Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package Note 1: Input reference clock can be the base frequency shown divided by “Mfin”, as...