Description
Pin Names OE# CLK LE Ax Yx VDD GND Description Output Enable Input (Active Low) Clock Input Latch Enable Input Data Input Data Outputs Supply Voltage Ground
Block Diagram
OE# CLK LE A1 1D C1 CK Y1
To 17 Other Channels
0713
09/23/02
ADVANCE INFORMATION documents contain information on prod
Features
- Meets JESD 82-2 specification.
- Internal series resistors to reduce switching noise.
- ±12 mA device capability.
- Low voltage operation - VDD = 3.3 ± 0.3V.
- 0.50 mm pitch, 56-Pin TSSOP package 1
Pin Configurations
NC NC Y1 GND Y2 Y3 VDD Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VDD Y16 Y17 GND Y18 OE# LE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34.
ICS162835 Datasheet
