Integrated Circuit Systems ICS650-07C
The ICS650-07C is a low cost, low jitter, high performance clock synthesizer for networking applications. The ICS650-07C outputs all have 0 ppm synthesis error.| Part No. | ICS650-07C |
|---|---|
| Datasheet | ICS650-07C Download |
| Manufacturer |  Integrated Circuit Systems |
| Description | Networking Clock Source |
| Buy | Stock & Price |
DESCRIPTION
Using analog Phase-Locked Loop (PLL) techniques, the device accepts a 12.5 MHz or 25.00 MHz clock or fundamental mode crystal input to produce multiple output clocks for networking chips, PCI devices, SDRAM, and ASICs. See the MK74CB214, ICS551, and ICS552-01 for non-PLL buffer devices which produce multiple low-skew copies of these output clocks. See the ICS570, ICS9112-16/17/18 for zero delay buffers that can synchronize outputs and other needed clocks.FEATURES
● Packaged in 20 pin narrow (150 mil) SSOP (QSOP)● 12.5 MHz or 25.00 MHz fundamental crystal or clock input
● Six output clocks with selectable frequencies
● SDRAM frequencies of 67, 83, 100, and 133 MHz
● Buffered crystal reference output
● Zero ppm synthesis error in all clocks
● Ideal for PMC-Sierra’s ATM switch chips
● Full CMOS output swing with 25 mA output drive capability at TTL levels
● Advanced, low power, sub-micron CMOS process
● 3.0V to 5.5V operating voltage Block Diagram VDD GND 2 2 2 Output Buffer...
