ICS650-36 Datasheet | Integrated Circuit Systems

Networking & PCI Clock Source Description The ICS650-36 is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental mode, inexpensive crystal input of 25 MHz to produce four output clocks supporting LAN, PCI, and 100M SDRAM functions. The device also has a power down feature that tri-states the clock outputs and turns off the PLL when the PDTS pin is taken low. Features - - - - - - - - - - Packaged in 16-pin TSSOP Available in Pb (lead) free package Replaces multiple crystals and oscillators Input crystal or clock frequency of 25 MHz Fixed reference output frequency of 25 MHz Selectable output frequencies of 33.3, 33.333, 50, 66.666, 100, and 125 MHz Duty cycle of 40/60 Operating voltage of 3.3 V Advanced, low-power CMOS process Industrial and mercial temperature ranges Block Diagram VDD 3 S2:0 Select/ Control Circuit PLL1 CLK1 PLL2 CLK2 PLL3 X1/ICLK 25 MHz crystal input X2 Crystal Oscillator/ Clock Buffer CLK3 External capacitors may be required. 3 GND PDTS (all outputs and PLLs) MDS 650-36 D I n t e gra te d C i r c u i t S ys t e m s - 1 5 25 Race Street, San Jose, CA 9 5126 - Revision 030206 tel (408 ) 2 97-12 01 - .icst.co m ICS650-36 Networking & PCI Clock Source Pin...