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ICS671-15 - Low Skew Buffer

General Description

The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications.

The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques.

Key Features

  • Packaged in 24-pin TSSOP.
  • Input-output delay (±300 ps).
  • Two ZDB 66 MHz outputs from a 66 MHz input AGP clock.
  • Two ZDB 66 MHz outputs, plus four 33 MHz outputs from a 33 MHz input CPU clock.
  • Output-to-output skew is less than 250 ps.
  • Full CMOS outputs with 18 mA output drive capability at TTL levels (at 3.3 V).
  • Spread SmartTM technology works with spread spectrum clock generators.
  • Advanced, low-power, sub-micron CMOS pro.

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Datasheet Details

Part number ICS671-15
Manufacturer Integrated Circuit Systems
File Size 157.50 KB
Description Low Skew Buffer
Datasheet download datasheet ICS671-15 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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ICS671-15 ZERO DELAY, LOW SKEW BUFFER Description The ICS671-15 is a low-jitter, low-skew, high-performance zero delay buffer (ZDB) for high-speed applications. The device is designed using ICS’ proprietary low-jitter PLL (Phase-Locked Loop) techniques. The ICS671-15 includes a ZDB bank of four outputs running at 33 MHz, and two outputs at 66 MHz from the CPU PLL. This device also provides two 66 MHz zero delay clocks derived from the AGP PLL. In the zero delay mode, the rising edge of the input clock is aligned with the rising edges of the feedback clock. The ICS671-15 provides feedback clocks internally for www.DataSheet4U.com the CPU PLL and the AGP PLL, and with the lowest jitter.