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ICS8624 - 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER

General Description

The ICS8624 is a high performance, 1-to-5 Differential-to-HSTL zero delay buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.

The ICS8624 has two selectable clock input pairs.

Key Features

  • Fully integrated PLL.
  • 5 differential HSTL outputs.
  • Selectable differential CLKx, nCLKx input pairs.
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL.
  • Output frequency range: 31.25MHz to 700MHz.
  • Input frequency range: 31.25MHz to 700MHz.
  • VCO range: 250MHz to 700MHz.
  • External feedback for “zero delay” clock regeneration.
  • Cycle-to-cycle jitter: 25ps (maximum).

📥 Download Datasheet

Datasheet Details

Part number ICS8624
Manufacturer Integrated Circuit Systems
File Size 320.43 KB
Description 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Datasheet download datasheet ICS8624 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Integrated Circuit Systems, Inc. ICS8624 LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER FEATURES • Fully integrated PLL • 5 differential HSTL outputs • Selectable differential CLKx, nCLKx input pairs • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL • Output frequency range: 31.25MHz to 700MHz • Input frequency range: 31.25MHz to 700MHz • VCO range: 250MHz to 700MHz • External feedback for “zero delay” clock regeneration • Cycle-to-cycle jitter: 25ps (maximum) • Output skew: 25ps (maximum) • Static phase offset: ±100ps • 3.3V core, 1.