ICS9112-17 - Low Skew Output Buffer

Integrated Circuit Systems

General Description

General a The ICS9112-17 is a high performance, low skew, low jitter .D buffer.

zero delay It uses a phase lock loop (PLL) w technology to align, in both phase and frequency, the REF input with the CLKOUT signal.

Key Features

Zero input - output delay Frequency range 25 - 133 MHz (3.3V) High loop filter bandwidth ideal for Spread Spectrum.

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ICS9112-17 low skew output buffer by Integrated Circuit Systems - Datasheet Preview

Datasheet Details

Part number	ICS9112-17
Manufacturer	Integrated Circuit Systems
File Size	137.51 KB
Description	Low Skew Output Buffer
Datasheet	ICS9112-17 Datasheet

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Integrated Circuit Systems, Inc. S a t Description General a The ICS9112-17 is a high performance, low skew, low jitter .D buffer. zero delay It uses a phase lock loop (PLL) w technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute w speed high clocks in PC systems operating at speeds wfrom 25 to 133 MHz. ICS9112-17 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS9112-17 has two banks of four outputs controlled by two address lines.