ICS9112-17 Description
General a The ICS9112-17 is a high performance, low skew, low jitter .D buffer. zero delay It uses a phase lock loop (PLL) w technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute w speed high clocks in PC systems operating at speeds wfrom 25 to 133 MHz.
ICS9112-17 Key Features
- Zero input
- output delay Frequency range 25
- 133 MHz (3.3V) High loop filter bandwidth ideal for Spread Spectrum