ICS91305 Datasheet PDF - Integrated Circuit Systems High Performance Communication Buffer Specs

ICS91305 - High Performance Communication Buffer

Datasheet Summary

Description

The ICS91305 is a high performance, low skew, low jitter clock driver.

It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal.

Features

Zero input - output delay Frequency range 10 - 133 MHz (3.3V) 5V tolerant input REF High loop filter bandwidth ideal for Spread Spectrum.

Datasheet Details

Part number	ICS91305
Manufacturer	Integrated Circuit Systems
File Size	122.00 KB
Description	High Performance Communication Buffer
Datasheet	ICS91305 Datasheet
Additional preview pages of the ICS91305 datasheet.

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Full PDF Text Transcription

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Integrated Circuit Systems, Inc. ICS91305 High Performance Communication Buffer General Description The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. ICS91305 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. The ICS91305 comes in an eight pin 150 mil SOIC package. It has five output clocks.

Published: Feb 9, 2010 |