ICS9248-20 Datasheet | Integrated Circuit Systems

Integrated Circuit Systems, Inc. Pentium/Pro TM System Clock Chip General Description The ICS9248-20 is a Clock Synthesizer chip for Pentium and Pentium Pro CPU based Desktop/Notebook systems that will provide all necessary clock timing. Features include four CPU and eight PCI clocks. Three reference outputs are available equal to the crystal frequency. Additionally, the device meets the Pentium power-up stabilization requirement, assuring that CPU and PCI clocks are stable within 2ms after power-up. PD# pin enables low power mode by stopping crystal OSC and PLL stages. Other power management Features include CPU_STOP#, which stops CPU (0:3) clocks, and PCI_STOP#, which stops PCICLK (0:6) clocks. High drive CPUCLK outputs typically provide greater than 1 V/ns slew rate into 20p F loads. PCICLK outputs typically provide better than 1V/ns slew rate into 30p F loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates. The ICS9248-20 accepts a 14.318MHz reference crystal or clock as its input and runs on a 3.3V core supply. Features • • • • • • • • • • • Generates system clocks for CPU, IOAPIC, PCI, plus 14.314 MHz REF (0:2), USB, and Super I/O Supports single or dual processor systems Supports Spread Spectrum modulation for CPU & PCI clocks, down spread -0.5% Skew from CPU (earlier) to PCI clock (rising edges for 100/33.3MHz) 1.5 to 4ns Two fixed outputs at 48MHz. Separate 2.5V and 3.3V supply pins 2.5V or 3.3V output: CPU, IOAPIC 3.3V outputs: PCI, REF, 48MHz No power supply sequence requirements Uses external 14.318MHz crystal, no external load cap required for CL=18p F crystal 48 pin 300 mil SSOP Block Diagram Pin Configuration 48-Pin SSOP Power Groups VDD = Supply for PLL core VDD1 = REF (0:2), X1, X2 VDD2 = PCICLK_F, PCICLK (0:6) VDD3 = 48MHz0, 48MHz1 VDDL1 = IOAPIC (0:1) VDDL2 = CPUCLK (0:3) 9248-20 Rev B 12/03/98 Ground Groups GND = Ground for PLL core GND1 = REF (0:2), X1, X2 GND2 =...