MK1491-14 Datasheet PDF - Integrated Circuit Systems OPTi ACPI Firestar Clock Source Specs

MK1491-14 - OPTi ACPI Firestar Clock Source

This page provides the datasheet information for the MK1491-14, a member of the MK1491E-14 OPTi ACPI Firestar Clock Source family.

Datasheet Summary

Description

The MK1491-14 is a low cost, low jitter, high performance clock synthesizer for OPTi’s Firestar and Firestar+ chipsets for Pentium™ Processor-based mobile computer applications.

Features

Packaged in 28 pin, 150 mil wide SSOP.
Provides all critical timing for OPTi ACPI Firestar and Firestar+.
Early Host clock of 3.5ns.
Separate VDD and skew adjust for Host 5,6, and 7 supports field upgrade to Firestar+ and new 2.5V processors.
48MHz USB, 24MHz SIO, and Audio clock support.
Single pin CPU(Host) slowdown to 33.3MHz.
Multiple power down modes.
Low EMI Enable pin reduces EMI radiation (patent pending) Block Dia.

Datasheet Details

Part number	MK1491-14
Manufacturer	Integrated Circuit Systems
File Size	91.01 KB
Description	OPTi ACPI Firestar Clock Source
Datasheet	MK1491-14 Datasheet
Additional preview pages of the MK1491-14 datasheet.

📁 Similar Datasheet

MK1493-02A - Networking/pci Clock Generator (Integrated Circuit System)

MK1417 - S3 Notebook Clock Source (MicroClock)

MK1417S - S3 Notebook Clock Source (MicroClock)

MK1417STR - S3 Notebook Clock Source (MicroClock)

MK1040VP - High Power RF LDMOS FET (Innogration)

MK10DN128VFM5 - Microcontroller (Freescale Semiconductor)

MK10DN32VFM5 - Microcontroller (Freescale Semiconductor)

MK10DN64VFM5 - Microcontroller (Freescale Semiconductor)

MK10DX128VFM5 - Microcontroller (Freescale Semiconductor)

MK10DX32VFM5 - Microcontroller (Freescale Semiconductor)

Full PDF Text Transcription

Click to expand full text

www.DataSheet4U.com MK1491-14 OPTi ACPI Firestar Clock Source Description The MK1491-14 is a low cost, low jitter, high performance clock synthesizer for OPTi’s Firestar and Firestar+ chipsets for Pentium™ Processor-based mobile computer applications. Using analog Phase-Locked Loop (PLL) techniques, the device uses a 14.318 MHz crystal input to produce multiple output clocks up to 75 MHz. It provides selectable Host and PCI local bus clocks as well as selectable clocks for Super I/O or Universal Serial Bus (USB). The device has up to seven Host output clocks. The chip has three different power down modes that reduce power on various clocks. Features • Packaged in 28 pin, 150 mil wide SSOP • Provides all critical timing for OPTi ACPI Firestar and Firestar+ • Early Host clock of 3.

Published: Jan 17, 2007 |