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MK2049-36 - 3.3 V Communications Clock PLL

General Description

The MK2049-36 is a Phase-Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies.

With an 8 kHz clock input as a reference, the MK2049-36 generates T1, E1, T3, E3, OC3/3, Gigabit Ethernet, and other communications frequencies.

Key Features

  • Packaged in 20 pin SOIC.
  • 3.3 V ±5% operation.
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E.
  • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz.
  • Locks to 8 kHz ±100 ppm (External mode).
  • Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.5 or x1/x2 outputs.
  • Exact internal ratios enable zero ppm err.

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Datasheet Details

Part number MK2049-36
Manufacturer Integrated Circuit Systems
File Size 125.95 KB
Description 3.3 V Communications Clock PLL
Datasheet download datasheet MK2049-36 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PRELIMINARY INFORMATION MK2049-36 3.3 V Communications Clock PLL Features • Packaged in 20 pin SOIC • 3.3 V ±5% operation • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz • Locks to 8 kHz ±100 ppm (External mode) • Buffer Mode allows jitter attenuation of 10-50 MHz input and x1/x0.5 or x1/x2 outputs • Exact internal ratios enable zero ppm error • Output clock rates include T1, E1, T3, E3, and OC3 submultiples • See the MK2049-01, -02, and -03 for more selections at VDD = 5 V, and the MK2049-34 for more selections at 3.