PA7128 Overview
The PA7128 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology. PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs. The PA7128 offers a versatile logic array architecture with 12 I/O pins, 14 input pins and 36 registers/latches (12 buried...
PA7128 Key Features
- Reprogrammable in 28-pin DIP , SOIC and PLCC packages Versatile Logic Array Architecture
- 12 I/Os, 14 inputs, 36 registers/latches
- Up to 36 logic cell output functions
- PLA structure with true product-term sharing
- Logic functions and registers can be I/O-buried Flexible Logic Cell
- Up to 3 output functions per logic cell
- D,T and JK registers with special features
- Independent or global clocks, resets, presets, clock polarity and output enables
- Sum-of-products logic for output enables High-Speed mercial and Industrial Versions
- As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX)