FEATURES
s CMOS Electrically Erasable Technology − Reprogrammable in 28-pin DIP , SOIC and PLCC packages Versatile Logic Array Architecture − 12 I/Os, 14 inputs, 36 registers/latches − Up to 36 logic cell output functions − PLA structure with true product-term sharing − Logic functions and registers can be I/O-buried Flexible Logic Cell − Up to 3 output functions per logic cell − D,T and JK registers with special features − Independent or global clocks, resets, presets, clock polarity and output enables − Sum-of-products logic for output enables High-Speed Commercial and Industrial Versions s − As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX) − Industrial grade available for 4.5 to 5.5V Vcc and -40 to +85 °C temperatures Ideal for Combinatorial, Synchronous and Asynchronous Logic APPLICATIONS
− Integration of multiple PLDs and random logic − Buried counters, complex state-machines − Comparitors, decoders, other wide-gate functions Development and Programmer Support − ICT PLACE Development Software − Fitters for ABEL, CUPL and other software − Programming support by ICT PDS-3 and other popular third-party programmers.
