PA7128 Datasheet PDF - Integrated Circuit Technology Programmable Electrically Erasable Logic Array Specs

PA7128 - Programmable Electrically Erasable Logic Array

Datasheet Summary

Description

The PA7128 is a member of the Programmable Electrically Erasable Logic (PEEL™) Array family based on ICT’s CMOS EEPROM technology.

PEEL™ Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today’s programmable logic designs.

Features

s CMOS Electrically Erasable Technology.
Reprogrammable in 28-pin DIP , SOIC and PLCC packages Versatile Logic Array Architecture.
12 I/Os, 14 inputs, 36 registers/latches.
Up to 36 logic cell output functions.
PLA structure with true product-term sharing.
Logic functions and registers can be I/O-buried Flexible Logic Cell.
Up to 3 output functions per logic cell.
D,T and JK registers with special features.
Independent or g.

Datasheet Details

Part number	PA7128
Manufacturer	Integrated Circuit Technology
File Size	257.05 KB
Description	Programmable Electrically Erasable Logic Array
Datasheet	PA7128 Datasheet
Additional preview pages of the PA7128 datasheet.

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Full PDF Text Transcription

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Commercial/ Industrial PA7128 PA7128 PEELTM Array Programmable Electrically Erasable Logic Array Features s CMOS Electrically Erasable Technology − Reprogrammable in 28-pin DIP , SOIC and PLCC packages Versatile Logic Array Architecture − 12 I/Os, 14 inputs, 36 registers/latches − Up to 36 logic cell output functions − PLA structure with true product-term sharing − Logic functions and registers can be I/O-buried Flexible Logic Cell − Up to 3 output functions per logic cell − D,T and JK registers with special features − Independent or global clocks, resets, presets, clock polarity and output enables − Sum-of-products logic for output enables High-Speed Commercial and Industrial Versions s − As fast as 9ns/15ns (tpdi/tpdx), 83.3MHz (fMAX) − Industrial grade available for 4.5 to 5.

Published: Jan 10, 2011 |