Integrated Device Technolog ICSLV810
The ICSLV810 is a low skew 1.5 V to 2.5 V, 1:10 fanout buffer. This device is specifically designed for data communications clock management. The large fanout from a single input line reduces loading on the input clock.DESCRIPTION
The TTL level outputs reduce noise levels on the part. Typical applications are clock and signal distribution. ICSLV810FEATURES
● Packaged in 20-pin QSOP/SSOP● Split 1:10 fanout Buffer
● Maximum skew between outputs of different packages
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● 0.75 ns Max propagation delay of 3.8 ns Operating voltage of 1.5 V to 2.5 V on Bank A Operating voltage of 1.5 V to 2.5 V on Banks B and C Advanced, low power, CMOS process Industrial temperature range -40° C to +85° C 3.3 V tolerant input when VDDA=2.5 V Pb (lead) free packaging Block Diagram r e .n a ww 1 t e n VDDA ua VDDB VDDC F w C CLKIN PD IDT™ / ICS™ BUFFER/CLOCK DRIVER ce. 8 c T CLK 1 CLK 2 CLK 3 CLK 4 CLK 5 CLK 6 CLK 7 CLK 8 CLK 9 CLK 10 om ICSLV810 REV H 051310 ria l ICSLV810 BUFFER/CLOCK DRIVER FAN OUT BUFFER Pin Assignment CLKIN GND CLK 1 VDDA CLK 2 GND CLK 3 VDDA CLK 4 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDDB CLK 10 CLK 9 GND CLK 8 VDDC CLK 7 GND CLK 6 CLK 5 20 pin (150mil) SSOP 2 3 4 5 6 7 8...