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ICS854S204I Datasheet Lvpecl Fanout Buffer

Manufacturer: Integrated Device Technology

Overview: LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER ICS854S204I.

General Description

The ICS854S204I is a low skew, high performance IC S dual, programmable 1-to-2 Differential-to-LVDS, HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClock S™ family of High Performance Clock Solutions from IDT.

The PCLKx, nPCLKx pairs can accept most standard differential input levels.

With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels.

Key Features

  • Two programmable differential LVDS or LVPECL output banks.
  • Two differential clock input pairs.
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML.
  • Maximum output frequency: 3GHz.
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx inputs.
  • Output skew: 15ps (maximum).
  • Bank skew: 15ps (maximum).
  • Propagation delay: 500ps (maximum).
  • Additive.

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ICS854S204I Distributor