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IDT54FCT16500CT - FAST CMOS 18-BIT REGISTERED TRANSCEIVER

Description

FCT16500AT/CT/ET and ABT16500 for on-board bus interThe FCT16500AT/CT/ET and FCT162500AT/CT/ET 18- face applications.

Features

  • FCT16500AT/CT/ET: simplifies layout. All inputs are designed with hysteresis for.
  • High drive outputs (-32mA IOH, 64mA IOL) improved noise margin.
  • Power off disable outputs permit “live insertion” The FCT16500AT/CT/ET are ideally suited for driving.
  • Typical VOLP (Output Ground Bounce) < 1.0V at high-capacitance loads and low-impedance backplanes. The VCC = 5V, TA = 25°C output buffers are designed with power off disable capability.
  • Features for FCT162500AT/CT/.

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Datasheet preview – IDT54FCT16500CT

Datasheet Details

Part number IDT54FCT16500CT
Manufacturer Integrated Device Technology
File Size 122.55 KB
Description FAST CMOS 18-BIT REGISTERED TRANSCEIVER
Datasheet download datasheet IDT54FCT16500CT Datasheet
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Full PDF Text Transcription

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FAST CMOS 18-BIT REGISTERED TRANSCEIVER Integrated Device Technology, Inc. IDT54/74FCT16500AT/CT/ET IDT54/74FCT162500AT/CT/ET bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power 18-bit reg• Common features: istered bus transceivers combine D-type latches and D-type – 0.5 MICRON CMOS Technology flip-flops to allow data flow in transparent, latched and clocked – High-speed, low-power CMOS replacement for modes. Data flow in each direction is controlled by outputABT functions enable (OEAB and OEBA), latch enable (LEAB and LEBA) – Typical tSK(o) (Output Skew) < 250ps and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, – Low input and output leakage ≤1µ A (max.) the device operates in transparent mode when LEAB is HIGH.
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